The invention generally relates to integrated circuits that employ latches or flip-flops, and more particularly to pulsed latch circuits.
Integrated circuits such as microprocessors and other integrated circuits employ combinational logic whose output is latched by flip-flops or latch circuits. The output of a latch circuit then serves as input to other combination logic and so on. In high performance chip designs, it is important for such synchronous designs to minimize the sequential overhead amongst the delays in the combinational logic and the flip-flops. The clock period to the flip-flops is increasingly becoming shorter and shorter to increase the speed of operation of the integrated circuit. As the combinational logic is getting more complex and the latch circuits between them operate on smaller clock pulses, process variations from the manufacturing process, which can increase or vary the hold time required for a latch to latch the incoming data from combinational logic, are becoming problematic. However, as the clock pulse or strobe pulse is narrowed, the resulting silicon can be more susceptible to process variations. The clocking must be set up so that it can allow the combinational logic to perform its functions and provide an output that is latched by the flip-flop.
The latch or registers between the combinational logic need to have their latch delays minimized in order to maximize the speed of operation of the IC. The setup time and hold time require a trade off and a known pulsed latch circuit uses a pulse generator to create a narrow pulse for the latch. An increase in the width of the pulse or strobe can degrade the hold time for the latches. However, attempting to narrow the strobe can result in the collapse of the circuit so there is no clock signal to the registers (flip-flops). Widening the pulse width results in increasing the hold times and causes a chip functional failure, however.
FIG. 1 illustrates one example of a prior art pulsed latch circuit. The prior art pulsed latch circuit 100 employs a pulse generator 102 that includes a variable delay circuit 104 that receives an input clock signal 106 and generates a strobe signal 108. The variable delay circuit 104 controls the width of the strobe signal 108. An input node 110 receives the incoming signal to be latched from combinational logic and an output node 112 provides the latched output signal to other combinational logic. The pulsed flip-flop 100 includes a keeper circuit 114 that retains the state of the flop when the clock signal is inactive. The transmission gate circuit 118 includes a transmission gate 120, inverter 122 and inverter 124 connected as shown. The transmission gate output node 126 is the latched input signal from input node 110. A problem arises when a very narrow pulse is provided by the pulse generator in order to meet speed requirements since the response to the various circuit components may be affected by process variations in the manufacturing process. Changing the variable delay to increase the pulse width makes the hold time of the flop or register very large so for short paths within a circuit in a sequential arrangement, where the data is arriving very early, having the hold time too large can unnecessarily increase the padding or waiting time between sequential sections and slow down the performance speed of the integrated circuit unnecessarily.
Accordingly, a need exists for an improved pulsed latch circuit.